This application claims the benefit of Korean Patent Application No. 2000-17903, filed Apr. 6, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to design and layout of integrated circuits and, more particularly, to design and layout of integrated circuits that include circuits comprising standard and/or non-standard cells.
An integrated circuit (IC) is typically designed by generating a circuit diagram first and then designing a layout based on the circuit diagram. In the layout, material layers such as a conductive layer, a semiconductor layer, and an insulating layer are formed of predetermined patterns to create each circuit element of the circuit diagram. Each of the predetermined patterns may also be horizontally and/or vertically arranged. An IC having the desired functions may be produced by repeating the operations of stacking and patterning each material layer based on the layout. Conventional operations for design and layout of an IC will be described in more detail hereafter with reference to FIG. 1.
Operations begin by drawing the IC as a circuit diagram (block 10). The IC is typically drawn using units of cells and/or blocks in which basic elements, such as a transistor or a resistor, are enclosed in a predetermined functional unit using a design program having a graphical user interface. In non-memory integrated circuits, such as a microprocessor or an application specific integrated circuit (ASIC), an inverter or a logic gate, such as an AND gate, may comprise one cell. By contrast, in memory integrated circuits, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a block may comprise many transistors or logic gates (see, e.g., the clock buffer of FIG. 4). In particular, when a cell comprises a single logic gate, as is typically common in non-memory ICs, the cell may be referred to as a standard cell. When a cell comprises a plurality of elements that are not enclosed in a single logic gate, however, the cell may be referred to as a non-standard cell. Thus, a circuit diagram of a memory IC is typically drawn using blocks that comprise standard and non-standard cells. The circuit diagram of an IC may be expressed as a set of symbols having an electrical meaning and the underlying circuit of each cell or block (i.e., the circuit at the transistor level) is generally referred to as a schematic circuit.
Once a circuit diagram for an IC is designed, operations of the IC may be simulated based on the circuit diagram to verify whether the IC operates properly. If the simulation results indicate that the IC does not operate properly, then the circuit diagram may be corrected. After the circuit diagram has been designed and simulated, the layout in each cell or block is designed (block 11). More specifically, each cell or block is laid out by designing material patterns having an actual physical meaning based on the schematic circuit of each cell or block. Moreover, relationships are established between the horizontal and vertical positions of the material patterns. Standard layouts typically exist for the underlying circuits that comprise standard cells; therefore, layout operations may be automated using a layout design tool. Unfortunately, non-standard cells are typically laid out manually. Because memory ICs typically include non-standard cells, the most time consuming operation in designing memory ICs is typically the layout of the individual blocks.
When the initial layout of each cell or block is completed, each cell or block may be arranged in the restricted size of an actual chip, and a cell layout abstraction model or block layout abstraction model having information used to connect the cells or blocks is generated (step 12). The cell or block layout abstraction model may include the size of the cell or block, the available positions of input/output pins connected to another cell or block, and obstruction(s) (e.g., a dummy pattern), through which an interconnection for connecting the cells or blocks can not pass.
Next, the placement and routing of each cell or block are performed based on the cell or block layout abstraction model (step 13). Conventionally, the placement and routing is performed using an automated tool. After placing and routing each cell or block, the design and layout of the IC is complete.
As ICs become more highly integrated, parasitic capacitance or resistance between interconnections for connecting cells or blocks may affect the performance of the ICs. Therefore, the parasitic capacitance and resistance between the interconnections for connecting the cells or blocks are calculated based on the layout in which the placement and routing of the cells or blocks has been completed (block 14). If the parasitic capacitance and/or resistance deviate from a predetermined reference value, then operations continue at block 10 where the circuit diagram is corrected, and the operations of blocks 11 through 14 are repeated. As a result, operations for laying out the cells or blocks are performed again as the previous layout may generally not be reused. Because these cell or block layout operations may be time consuming, especially for non-standard cells, the overall time to design and layout the IC may significantly increase.
According to embodiments of the present invention, an integrated circuit (IC) is designed by generating a circuit diagram of the IC using a first plurality of blocks. An information repository is provided that comprises layout information that is associated with one or more template blocks. A symbol layout abstraction model is then generated by associating the layout information that is associated with one or more of the template blocks with at least one of the first plurality of blocks that comprise the circuit diagram of the IC. The symbol layout abstraction model may include size information and/or pin position information, which may be used in arranging the blocks and/or determining routing paths for interconnections between the pins of the various blocks. A block may comprise non-standard cells, which may be designed and laid out manually in a time intensive process. Advantageously, the information repository may allow the symbol layout abstraction model to be generated without first performing a design layout for the underlying cells that comprise the circuit diagram blocks.
The layout information that is respectively associated with the template blocks may comprise one or more of the following types of information: size information, pin position information, obstruction information, information related to the numbers of circuit elements contained in a template block, and information related to the sizes of these circuit elements.
In accordance with further embodiments of the present invention, after the symbol layout abstraction model is generated, an initial arrangement of the first plurality of blocks may be generated and initial interconnections between the blocks may be determined based on the symbol layout abstraction model. A parasitic capacitance and/or a resistance for one or more of the interconnections may then be estimated and a determination made whether the parasitic capacitance and/or resistance are within a predetermined reference value. If the parasitic capacitance and/or resistance is not within the predetermined reference value, then a revised circuit diagram of the IC may be generated using a second plurality of blocks and the operations discussed above may be repeated for the revised circuit diagram.
If the parasitic capacitance and/or resistance is within the predetermined reference value, then, in accordance with further embodiments of the present invention, a design layout may be performed for the first plurality of blocks by designing material patterns for the respective blocks based on the circuit diagram. An actual layout abstraction model may then be generated that comprises layout information associated with the respective material patterns. The layout information may comprise size information, pin position information, and/or obstruction information.
In accordance with still further embodiments of the present invention, a final arrangement of the first plurality of blocks may be generated based on the initial arrangement of the first plurality of blocks and the actual layout abstraction model. In addition, final interconnections may then be determined between the first plurality of blocks based on the initial interconnections and the actual layout abstraction model.
In accordance with further embodiments of the present invention, the material patterns for the respective first plurality of blocks may be designed and the actual layout abstraction model may be generated in parallel with generating the symbol layout abstraction model, generating the initial arrangement of the first plurality of blocks, determining the initial interconnections, estimating the parasitic capacitance and/or the resistance for one or more of the initial interconnections, and/or determining whether the estimate is within the predetermined reference value.
In summary, the present invention may allow the symbol layout abstraction model for each block to be generated directly from the IC circuit diagram though use of an information repository that comprises template blocks with associated size and/or pin position information. Furthermore, the present invention may allow the blocks to be arranged, routes for interconnections between the blocks to be defined, and/or corrections of the schematic circuit to be performed without designing actual layouts for the blocks. Accordingly, the time required to design and layout an IC may be reduced.